Job Description
Job Requirements:
Bachelor’s in EE/ECE (or a related field). 10 years in APR layout implementation and CAD/automation development. Deep CMOS layout knowledge across planar/FinFET/GAA, incl. DRM/DFM. Expert PV/debugging (Caliber, PVS, or equivalent). Strong scripting: Python, Tcl, SKILL, Perl. Knowledge of floorplanning/power mesh/critical routing/hierarchical integration. Strong cross-team communication. Hands-on proficiency with APR tools: Cadence Innovus, Synopsys ICC2, and/or Fusion Compiler. Plus: AI/Agentic AI in EDA, Foundation IP (IO/ESD), RF/Analog layout, SI/PI, EM/IR.
Technical Manager – NPU Physical Design (APR & CAD Automation)
Location: Singapore
Employment Type: Full-Time
Industry: Semiconductor | AI Hardware | ASIC | VLSI | EDA
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