STA Engineer: Timing Closure for Complex SoCs

UST Malaysia is seeking an experienced engineer to ensure timing closure for complex ASIC/SoC designs. You will perform static timing analysis across the design cycle and collaborate with RTL, synthesis, physical design, DFT, and signoff teams to optimize timing, power, and area while meeting performance targets.

The role requires 3+ years of experience and a strong foundation in digital IC design, STA methodologies, and scripting.