Senior Sta Timing Engineer (Meta)

Meet the team. Join our dynamic Test Timing Engineering team, a group of passionate experts dedicated to ensuring robust and accurate timing constraints for advanced chip designs. Our work is critical to the success of the broader silicon design process, enabling efficient test and verification of complex integrated circuits.

Responsibilities

• Own the creation and validation of timing constraints at block, sub-chip, and full-chip levels in various test modes.
• Perform quality checks, including identifying duplicated constraints and verifying unconstrained endpoints, to drive robust timing analysis.
• Develop and enhance methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows.
• Collaborate with cross-functional teams to resolve timing and design flow issues, accelerating project execution.
• Implement and maintain SDC flows and validation processes to ensure compliance and accuracy across all ...