Senior Principal SOC Design Engineer: RTL & Low-Power

MaxLinear Asia Singapore Private Limited is searching for an Electronics Engineer to develop VHDL and Verilog solutions. You will engage in RTL coding and SoC integration, working alongside various teams to enhance verification processes.

The ideal candidate should possess at least 18 years of experience in Electronic Engineering, with strong expertise in multi-million gate IP development and problem-solving skills in a collaborative environment.