Senior Front-End ASIC RTL/Logic Lead

Altera is seeking a seasoned engineer for leading high-speed digital design projects in Penang, Malaysia. Ideal candidates should have a BS/MS or PhD in Electronics Engineering with at least 10 years of ASIC frontend experience. Responsibilities include collaborating with verification and back-end teams, and supporting post-silicon debug.

Proficiency in RTL coding with HDL and familiarity with tools like Spyglass, Synthesis, and STA are essential. Strong leadership and analytical skills are crucial for this role.