Senior Design Verification Engineer (SystemVerilog UVM)

We are looking for a Senior Functional Verification Engineer to join our growing team. The ideal candidate brings deep expertise in SystemVerilog and UVM methodology, a strong track record of leading verification efforts from spec to sign-off, and the ability to mentor junior engineers and drive verification strategy across projects.

Responsibilities

Architect and own UVM-based testbench frameworks for block-level and system-level verification. Define and drive verification plans, coverage models, and sign-off criteria in collaboration with design and architecture teams. Develop and review constrained-random test scenarios, functional coverage, and SystemVerilog Assertions (SVA). Lead debug sessions, identify root causes of complex simulation failures, and provide clear direction to the team. Review RTL specifications and contribute to DV methodology decisions and best practices. Mentor Semi‑Senior and Junior engineers, conducting code and testplan revie...