Senior Analog Layout Engineer: From Block to Chip Design

Infineon Technologies Malaysia seeks an experienced engineer to perform analog circuit block, subsystem, and top‑level layout and verification using state‑of‑the‑art tools, including Cadence Virtuoso‑VXL.

You will participate in layout design of analog circuits, plan floor‑planning from scratch, and handle routing, verification and violations while contributing to design reviews. 2–5 years of hands‑on analog layout experience in sub‑micron CMOS is expected.