Senior AI/In-Memory ASIC RTL Engineer

TetraMem INC in Singapore is looking for a talented engineer with expertise in RTL design and validation for ASIC/SoC products. The role involves responsibilities such as simulation, IP integration, and mentoring junior engineers.

The ideal candidate holds an MS with significant experience or a PhD in Electrical Engineering, with proficiency in Verilog and System Verilog. Experience in FPGA/ASIC design and the ability to offer technical leadership are highly valued.