Semiconductor Layout & Verification Engineer

Block Build PD

(Lead-8+ years)

* Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,

* Block level Physical Signoff,

* Block level Timing Signoff and ECO generation.

* Block level Power (EM/IR) signoff.

* Good skill on Automation (Perl/Tcl/Awk/Python)

* Able to provide technical guidance to Junior Engineer and lead 4-6 engineers.

* Must have led small project team.

* Good in communication skill as point of contact for client.

Block Build PD

(Individual Contributor-4+)

* Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,

* Block level Physical Signoff,

* Block level Timing Signoff and ECO generation.

* Block level Power signoff.

* Good skill on Automation (Perl/Tcl/Awk/Python)

Physical Verification (Full Chip-8+)

* Expe...