Physical design & flow methodology engineer

This role sits at the core of a high-performance processor IP team, owning PPA optimization, building scalable RTL-to-GDSII flows, and supporting customers through integration and tapeout. You will work across architecture, RTL, and physical design to drive real silicon outcomes and meet aggressive performance, power, and area targets across nodes.
Key Responsibilities
Drive PPA optimization across timing, area, leakage, and dynamic power
Apply low-power techniques and tune synthesis/P&R for aggressive targets
Build and maintain reusable RTL-to-GDSII reference flows
Develop automation using TCL/Python to improve flow efficiency
Collaborate with architecture and RTL teams to influence design trade-offs
Support customers from evaluation to tapeout, resolving implementation issues
Contribute to PPA modeling and feasibility analysis for pre-sales
Ideal Candidate
7+ years of ASIC / processor IP physical design experience with a strong focus on PPA optimization ...