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ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
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View JobDirector, Hardware Engineering | Photonics IC, SERDES, EIC, PIC, High Speed Wireline | 15+ years, Bangalore
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View JobASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)
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View JobPlatform Test Engineer - L2/L3 Protocols| Routing| Python Automation (8-12 yrs)
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View JobASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, Bangalore
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