Memory Interface PHY IP, Design Engineering Architect

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
A Design Engineering Architect provides the technical leadership needed to translate evolving standards and customer requirements into scalable, high‑quality IP architectures. This role reduces execution risk, accelerates customer engagements, and strengthens long‑term product competitiveness.


Design Engineering Architect – Roles & Responsibilities

+ Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations

+ Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements

+ Good understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs

+ Act as a customer‑facing technical architect during pre‑sal...