Lead ASIC RTL Engineer

Weekday AI · Bengaluru, Karnataka, India

Location
Bengaluru
Job Type
Full time
Posted
July 06, 2026

Job Description

This role is for one of Weekday’s clients

Min Experience: 8+ years
Location: Bengaluru, Karnataka
JobType: full-time

We need a strong RTL expert who can lead our silicon program to tapeout. You will be the technical bridge between our architecture and our design partner, owning every step from RTL freeze to GDSII handoff, working with our partners. You will also build and lead the RTL team of 5–7 engineers. This is a hands-on lead role. You write RTL, review RTL, run synthesis, and own the result. The architect defines what gets built. You own how it gets built.

Requirements

Responsibilities

  • Translate the architecture specification into synthesizable SystemVerilog
  • Own the RTL coding standards, linting rules, and design methodology
  • Lead a team of 5-7 RTL engineers through the full design cycle
  • Own the synthesis flow (Design Compiler or Genus) and drive timing closure
  • D...

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