Ip Verification Engineer Mts/Sde

Experience : 8 to 12 years Role Description This full-time on-site Lead - Design Verification role is based in Bengaluru. The responsibilities include planning, developing, and implementing comprehensive design verification strategies for IP, SOC, and ASIC Semiconductor designs. Responsibilities : Lead IP or SoC verification using UVM Develop/oversee C-based & UVM testbenches Define strategy, drive coverage closure & sign-off Debug complex issues & manage regressions Mentor and scale high-performing DV teams Must-have experience: Must have worked on DDR/LPDDR, PCIe, USB, Ethernet or SOC Strong in SystemVerilog, UVM, SVA, and C-based verification Proven SoC/IP verification expertise Tools: VCS / Xcelium / Questa Scripting Knowledge : C/Python/TCL Location Flexibility : Bangalore or Noida