IP Design Verification Engineer (DDR5/LPDDR5) - Hybrid

Intel in Malaysia, Penang, seeks an experienced IP Design Verification Engineer to verify LPDDR5 and DDR5 IPs for SoC applications. You will develop RTL validation, OVM/UVM testbenches, and verification strategies across RTL and GLS stages.

Collaborate with architects, RTL developers, and physical design teams to ensure protocol compliance, create BFMs, automate pre‑silicon flows with Tcl/Python, and contribute to verification infrastructure.