Innovative ISP RTL Design Engineer

A leading technology firm in Singapore is seeking an experienced engineer to implement ISP algorithms into hardware using Verilog, SystemVerilog, and/or SystemC. The ideal candidate will have a strong background in C/C++ programming and verification, along with excellent debugging and problem-solving skills. This role involves verifying logic at the ISP and Digital System levels, optimizing designs for efficiency, and collaborating closely with the ISP Algorithm Team. Competitive salary and benefits offered.
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