Hybrid FPGA Design Engineer: AI & 4K/8K Data Processing

Aistech Space in Sant Cugat del Vallès is seeking an expert FPGA Design Engineer to lead the development of image acquisition systems. You will optimize VHDL for Xilinx chips and manage the lifecycle of high-speed data.

The ideal candidate has a BSc or MSc in Electronics or Telecommunications, coupled with strong VHDL and high-speed hardware expertise. A flexible contract with competitive pay and benefits is offered, including hybrid work options and access to sports facilities.