[HW] NoC (Network-on-Chip) Design Engineer

About DeepX Co., Ltd. DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.

Responsibilities

• Design and implement NoC architecture for high-performance AI accelerators.
• Optimize on-chip interconnects for power, performance, and area (PPA).
• Conduct performance modeling and simulation to analyze throughput, latency, and congestion.
• Work closely with Architecture and Frontend teams to define bus protocols and interface specifications.
• Perform RTL coding, synthesis, and timing closure for NoC components.
• Develop verification strategies to ensure the robustness and scalability of the NoC design.

Qualifications

• Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience in RTL design (Verilog/SystemVerilog) for complex SoC environments.