FPGA IP Design Engineer II — RTL, SerDes & Protocols

Lattice Malaysia is looking for an IP Design Engineer who will focus on developing high-speed RTL designs for Connectivity IP portfolios. The successful candidate will closely collaborate with architects to ensure optimal performance and power efficiency in FPGA designs.

Ideal candidates will have at least 3 years of experience in FPGA IP design, along with strong programming skills. This role requires self-motivation and the ability to work under varying conditions.