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ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
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View JobASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)
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View JobPlatform Test Engineer - L2/L3 Protocols| Routing| Python Automation (8-12 yrs)
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View JobTechnical Leader - C/C++, Device Driver, Kernel, Multithreading, Embedded Systems - 10 to 13 years - Bangalore
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View JobSenior Embedded SE | C, Device Driver, Linux ,Multithreading - 7 to 10 years - Bangalore
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View JobASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
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