Digital ASIC Design Engineer for Print Systems

HP R&D Singapore seeks an experienced ASIC Design Engineer to contribute to digital ASIC components for printing systems, performing RTL implementation, verification, and system integration.

The candidate should have 3+ years in ASIC/SoC design, strong Verilog/SystemVerilog skills, and familiarity with Synopsys and Cadence toolchains, plus scripting and Git workflows. Knowledge of Inkjet/LaserJet architectures is advantageous.