Design Verification Lead

- Architect testbenches for PCIe Gen5/Gen6/Gen7 XTOR solutions on advanced FPGA /Asic platforms.- Develop new C++/UVM based test architectures for high performance datapaths and protocol engines.- Map complex PCIe/CXL test cases to the latest specifications.- Debug PCIe protocol issues across the transaction, data link, and physical layers.- Collaborate cross functionally with architecture, verification, and system teams to deliver production ready solutions.Required Experience- 10+ years of hands-on PCIe experience (Gen4/Gen5 required;
Gen6 strongly preferred).- Deep understanding of PCIe/CXL architecture and protocols, including:Transaction Layer, Data Link Layer, and Physical LayerLTSSM, flow control, equalization, and link trainingCache/Memory concepts, VLSM, credit flow, and enumerationStrong C++, System Verilog, and UVM skills.Experience with verification and validation flows.Strong lab debugging experience using protocol analyzers, oscilloscopes, and bring up tools.Prefer...