Design Verification engineer/Senior (System Verilog/UVM)

People Profilers · Ho Chi Minh City, Hồ Chí Minh, Vietnam

Location
Ho Chi Minh City
Job Type
Full-time
Posted
June 29, 2026

Job Description

Job Description:

Job Ref: QV79VR4R

Title: Design Verification Engineer


Location: Onsite in HCM City


Requirements:

4+ years experience with Design Verification


Strong experience with SystemVerilog


Strong experience developing test benches with UVM


Strong experience implementing test cases with UVM


Experience with standard interfaces such as I2C, UART, SPI, AMBA, AHB, USB, etc.


Experience with these interfaces is a bonus: PCIe, UCIe, CXL, Ethernet

Contact: Phuong Le - 0903432692 - [email protected] 

Required Skills:

Design

Ready to Apply?

Submit your application for Design Verification engineer/Senior (System Verilog/UVM) at People Profilers

Apply Now