Location
singapore
Job Type
Full-time
Posted
June 07, 2026
Job Description
Responsibilities
- Develop and maintain UVM-based verification environments for IP and SoC-level verification
- Define, implement, and execute verification test plans based on design and architecture specifications
- Develop SystemVerilog (SV) UVM test cases and testbench components for functional verification
- Perform simulation runs, debug RTL and testbench issues, and analyze functional failures
- Verify SoC subsystems including DMA/DMAC, SRAM memory controllers, interrupt systems, and fault management blocks
- Implement and validate fault injection scenarios, including ECC/parity error handling and interrupt propagation mechanisms
- Ensure correct behavior of interrupt systems (masking, prioritization, clearing)
- Perform coverage analysis (code and functional) and drive verification closure
- Work on AMBA protocol verification (APB, AHB, AXI), including burst transfers, pipelining, wait states, and pro...